Does coherence mean all caches always contain identical data?

No. Caches may hold different subsets and states. The protocol governs which copies can be used and how conflicting accesses are coordinated.

Is a coherent counter increment automatically atomic?

No. The read, calculation and write need the appropriate atomic or synchronization mechanism.

Can independent variables still cause coherence traffic?

Yes. If writers on different cores modify variables in the same cache line, false sharing can occur.

AI Glossary / Data engineering and architecture / Intermediate

Cache coherence

Definition

Cache coherence is the coordination that keeps cached copies of shared memory locations consistent with the system's rules for reads and writes. In a multicore processor, it prevents independent caches from indefinitely treating conflicting versions of the same location as valid.

What it means

Processors use caches because accessing nearby cached data is generally faster than repeatedly fetching it from main memory. Several cores may therefore hold copies of the same memory region. When one core changes that region, the system needs rules for handling the other copies.

Coherence is about those copies and the ordering of accesses to a given location. It is not a guarantee that every cache contains an identical snapshot at every instant. A cache may have no copy, a valid shared copy or a modified copy whose data has not yet been written back to main memory.

It also differs from the broader memory consistency model, which governs how operations across locations can be observed. A coherent machine still requires correctly designed synchronization in programs that share mutable state.

How it works

Coherence protocols track states and exchange messages when cores access shared cache lines. A line is the block of memory managed by the cache, rather than necessarily one application variable. In an invalidation-based design, a core obtaining permission to modify a shared line causes other cached copies to become invalid.

A later reader must obtain an appropriate current copy instead of using an invalid one. The data may come through another cache or the memory hierarchy, depending on the implementation. Snooping and directory-based mechanisms are common approaches to tracking or discovering relevant copies.

MESI names four familiar states: Modified, Exclusive, Shared and Invalid. Other protocols extend or change this scheme. The details affect performance, but programmers normally use the language and platform's locks, atomics and synchronization facilities rather than manually implementing the hardware coherence protocol.

Three practical examples

Two processor cores communicate through shared data while their cache system coordinates valid copies of the underlying memory lines.
A performance engineer investigates why several threads updating nearby counters generate excessive coherence traffic.
A device-driver developer checks whether a particular DMA path is coherent and follows the platform's required memory-management interface.

Think of it this way

Think of several colleagues consulting copies of a working document, with a coordinator tracking who may edit and which copies are no longer valid. The coordination stops an old copy being treated as current after the relevant update has been established.

The analogy is limited: hardware operates on cache lines and precise protocols, not whole documents or human approval. It also does not make a multistep business action indivisible. Coordinating copies is different from coordinating an entire sequence of calculations.

Worked example

Consider two cores that both hold a shared cache line containing a counter with value 10. In an illustrative invalidation-based protocol, core A obtains the right to modify the line and core B's copy is invalidated. A writes 11. When B subsequently needs that line, it must acquire a valid version rather than continue using its invalid copy.

Now consider the separate operation “read the counter, add one, write the result”. Without an appropriate atomic operation or lock, two threads can both read 10 and both later write 11. The final result can lose one increment even though the cache-coherence system correctly coordinates the individual memory accesses.

This is a conceptual interleaving, not runnable code: some programming languages classify unsynchronized access of this kind as a data race with undefined behavior. The lesson is that coherence does not automatically make a read-modify-write sequence atomic.

Illustrative case study

Illustrative case study: A fictional image-processing team gives each worker its own progress counter. The counters are logically independent, but several occupy the same cache line. Repeated writes cause the line's ownership to move between cores, slowing progress reporting.

The team profiles the workload and tests a layout that separates frequently written worker data. It checks the memory cost and measures complete processing time rather than assuming padding always helps. The actual image algorithm still uses appropriate synchronization where workers share results.

This invented case illustrates false sharing: hardware coordinates at a larger granularity than the application's independent variables. It provides no benchmark result and does not imply that every pair of adjacent fields causes a performance problem.

Common misconceptions and mistakes

Assuming coherent caches remove the need for locks or atomic operations.
Confusing cache coherence with a complete ordering guarantee across all memory locations.
Assuming modified data must always reach main memory before another core can use it.
Ignoring false sharing between independent variables in the same line.
Assuming every peripheral or accelerator participates in the same coherence domain as the CPUs.

Business use

For businesses, cache coherence is usually relevant through application performance and correctness rather than a direct configuration choice. A server with more cores does not automatically accelerate a workload that repeatedly transfers ownership of shared data.

When scaling a multithreaded service, investigate contention and data layout alongside CPU utilization. Use representative workloads and platform-aware profiling. For AI systems involving CPUs, GPUs or other accelerators, establish which memory paths are coherent and which require explicit transfers or synchronization. Product documentation and supported programming interfaces determine those boundaries; the word “shared” alone is insufficient.

Check your understanding

Two threads each intend to increment 10 once but both read 10 before writing 11. Has a final value of 11 necessarily proved broken hardware coherence?

Answer: No. The multistep increment lacked the required atomic coordination. Hardware coherence alone does not make that sequence indivisible.

Related terms

CPU cache
Cache line
MESI
Memory consistency
Memory barrier
Atomic operation
False sharing
Directory protocol
Direct memory access

Learn next

Separate three questions: whether a cached copy is valid, whether operations occur in the required order and whether a compound operation is atomic. Then examine the language-level synchronization used by a small producer-consumer example.

Sources

Primary sources: Intel, Faster Core-to-Core Communications, coherence-state and messaging explanation: https://www.intel.com/content/www/us/en/developer/articles/technical/fast-core-to-core-communications.html ; Linux kernel documentation, memory barriers, CPU caches and DMA coherence: https://www.kernel.org/doc/html/latest/core-api/wrappers/memory-barriers.html . Relevant returned sections reviewed. Counter sequence and image-processing case are original conceptual examples; protocol details vary by architecture.

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